The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Mar. 17, 2023
Xidian University, Xi'an, CN;
Huiyong Hu, Xi'an, CN;
Liming Wang, Xi'an, CN;
Bin Shu, Xi'an, CN;
Bin Wang, Xi'an, CN;
Ningning Zhang, Xi'an, CN;
Tian Miao, Xi'an, CN;
Jian Zhang, Xi'an, CN;
Lingyao Meng, Xi'an, CN;
Maolong Yang, Xi'an, CN;
Xinlong Shi, Xi'an, CN;
Heming Zhang, Xi'an, CN;
Xidian University, Xi'an, CN;
Abstract
Provided are a CMOS structure, and fabrication methods of a FinFET CMOS, an FD CMOS and a GAA CMOS. The CMOS structure includes an nMOS and a pMOS, The nMOS includes a first channel region and a first gate electrode formed on a semiconductor substrate, and the pMOS includes a second channel region and a second gate electrode formed on the semiconductor substrate, where the first channel region and the second channel region are formed of semiconductor materials with the same conductivity type, and the first gate electrode and the second gate electrode are formed of the conductive materials with the same work function. This CMOS structure reduces the processing steps for fabricating the CMOS, thereby reducing the process complexity and the production cost, which is beneficial for improving the performance and reliability of CMOS and its integrated circuits.