The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Apr. 17, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Chih Huang, Hsinchu, TW;

Chi-Hui Lai, Taichung City, TW;

Ban-Li Wu, Hsinchu, TW;

Ying-Cheng Tseng, Tainan City, TW;

Ting-Ting Kuo, Hsinchu, TW;

Chih-Hsuan Tai, Taipei City, TW;

Hao-Yi Tsai, Hsinchu, TW;

Chuei-Tang Wang, Taichung City, TW;

Chung-Shi Liu, Hsinchu, TW;

Chen-Hua Yu, Hsinchu, TW;

Chiahung Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 95/00 (2026.01); H01G 4/00 (2006.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 74/15 (2026.01); H10W 90/28 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/117 (2026.01); H10W 95/00 (2026.01); H01G 4/00 (2013.01); H10W 72/241 (2026.01); H10W 72/874 (2026.01); H10W 72/884 (2026.01); H10W 72/9413 (2026.01); H10W 74/142 (2026.01); H10W 74/15 (2026.01); H10W 90/28 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/728 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01); H10W 90/794 (2026.01);
Abstract

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.


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