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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12622042 B1

PDFFull Text
Date of Patent:
May. 05, 2026

Filed:

May. 12, 2022

Multi-layered or graded gate dielectric in thin film transistor (tft) structures

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Anil Sharma, Portland, OR (US);

Albert B. Chen, Portland, OR (US);

Mark Armstrong, Portland, OR (US);

Afrin Sultana, Portland, OR (US);

Van H. Le, Beaverton, OR (US);

Travis W. Lajoie, Forest Grove, OR (US);

Shailesh Kumar Madisetti, Portland, OR (US);

Timothy Jen, Portland, OR (US);

Cheng Tan, Hillsboro, OR (US);

Moshe Dolejsi, Portland, OR (US);

Vishak Venkatraman, Portland, OR (US);

Christopher Ryder, Portland, OR (US);

Deepyanti Taneja, Happy Valley, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:

Arcane Law PLLC

Primary Examiner:

Nikolay K Yushin

Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 23/522 (2006.01); H01L 27/108 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 64/685 (2025.01); H01L 23/5226 (2013.01); H10B 12/30 (2023.02); H10D 30/6729 (2025.01); H10D 30/6755 (2025.01);
Abstract

Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

Find Patent Forward Citations

Sharma, Abhishek. (2026). Multi-layered or graded gate dielectric in thin film transistor (tft) structures (U.S. Patent No. 12622042). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12622042

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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