The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2026
Filed:
May. 12, 2022
Intel Corporation, Santa Clara, CA (US);
Abhishek Anil Sharma, Portland, OR (US);
Travis W. Lajoie, Forest Grove, OR (US);
Forough Mahmoudabadi, Beaverton, OR (US);
Shailesh Kumar Madisetti, Portland, OR (US);
Van H. Le, Beaverton, OR (US);
Timothy Jen, Portland, OR (US);
Cheng Tan, Hillsboro, OR (US);
Jisoo Kim, Portland, OR (US);
Miriam R. Reshotko, Portland, OR (US);
Vishak Venkatraman, Portland, OR (US);
Eva Vo, Beaverton, OR (US);
Yue Zhong, Portland, OR (US);
Yu-Che Chiu, Hillsboro, OR (US);
Moshe Dolejsi, Portland, OR (US);
Lorenzo Ferrari, San Diego, CA (US);
Akash Kannegulla, Hillsboro, OR (US);
Deepyanti Taneja, Happy Valley, OR (US);
Mark Armstrong, Portland, OR (US);
Kamal H. Baloch, Portland, OR (US);
Afrin Sultana, Portland, OR (US);
Albert B. Chen, Portland, OR (US);
Vamsi Evani, Hillsboro, OR (US);
Yang Yang, Portland, OR (US);
Juan G. Alzate-Vinasco, Tigard, OR (US);
Fatih Hamzaoglu, Portland, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.