Hillsboro, OR, United States of America

Yu-Che Chiu

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Corporation. Active years: 2026.

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Innovations of Yu-Che Chiu in Memory Structures

Introduction

Yu-Che Chiu is an accomplished inventor based in Hillsboro, OR (US). He has made significant contributions to the field of memory structures, particularly through his innovative patent. His work focuses on enhancing the performance and efficiency of memory devices.

Latest Patents

Yu-Che Chiu holds a patent for a "Multi-tier memory structure with graded characteristics." This patent outlines techniques for forming multi-tier memory structures that exhibit graded characteristics across different tiers. The memory structure includes memory cells, each comprising an access device and a storage device. The access device may utilize a thin film transistor (TFT) structure, while the storage device typically consists of a capacitor. The invention allows for the alteration of geometric or material parameters in a graded manner across multiple tiers, compensating for process effects that occur during fabrication. This innovation aims to enhance the performance of memory arrays across each tier.

Career Highlights

Yu-Che Chiu is currently employed at Intel Corporation, a leading technology company known for its advancements in semiconductor manufacturing and memory technologies. His work at Intel has positioned him as a key player in the development of next-generation memory solutions.

Collaborations

Yu-Che Chiu has collaborated with notable colleagues, including Abhishek Anil Sharma and Travis W LaJoie. These collaborations have contributed to the advancement of innovative technologies within the field.

Conclusion

Yu-Che Chiu's contributions to memory structure innovations reflect his expertise and commitment to advancing technology. His patent on multi-tier memory structures showcases his ability to address complex challenges in memory design.

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