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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12616011 B1

PDFFull Text
Date of Patent:
Apr. 28, 2026

Filed:

Jul. 21, 2022

Semiconductor device including a self-aligned contact layer with enhanced etch resistance

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

I-Ming Chang, Hsinchu, TW;

Yao-Sheng Huang, Hsinchu, TW;

Hsiang-Pi Chang, Hsinchu, TW;

Lo-Heng Chang, Hsinchu, TW;

Yun-Ju Fan, Hsinchu, TW;

Huang-Lin Chao, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Victoria K Hall

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76825 (2013.01); H01L 21/28518 (2013.01); H01L 21/76897 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 84/0147 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H01L 21/76831 (2013.01); H10D 64/017 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01);
Abstract

A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-aligned contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.

Find Patent Forward Citations

Chang, I-Ming. (2026). Semiconductor device including a self-aligned contact layer with enhanced etch resistance (U.S. Patent No. 12616011). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12616011

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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