The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2026
Filed:
Aug. 24, 2021
Intel Corporation, Santa Clara, CA (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Noriyuki Sato, Hillsboro, OR (US);
Van H. Le, Beaverton, OR (US);
Sarah Atanasov, Beaverton, OR (US);
Hui Jae Yoo, Hillsboro, OR (US);
Bernhard Sell, Portland, OR (US);
Pei-Hua Wang, Beaverton, OR (US);
Travis W. Lajoie, Forest Grove, OR (US);
Chieh-Jen Ku, Portland, OR (US);
Juan G. Alzate-Vinasco, Tigard, OR (US);
Fatih Hamzaoglu, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.