The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Sep. 23, 2021
Intel Corporation, Santa Clara, CA (US);
Stephen M. Cea, Hillsboro, OR (US);
Aaron D. Lilak, Beaverton, OR (US);
Patrick Keys, Beaverton, OR (US);
Cory Weber, Hillsboro, OR (US);
Rishabh Mehandru, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
Mohammad Hasan, Aloha, OR (US);
William Hsu, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Chang Wan Han, Hillsboro, OR (US);
Kihoon Park, Hillsboro, OR (US);
Sabih Omar, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.