The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Aug. 19, 2022
Intel Corporation, Santa Clara, CA (US);
Jimin Yao, Chandler, AZ (US);
Adel A. Elsherbini, Chandler, AZ (US);
Xavier Francois Brun, Hillsboro, OR (US);
Kimin Jun, Portland, OR (US);
Shawna M. Liff, Scottsdale, AZ (US);
Johanna M. Swan, Scottsdale, AZ (US);
Yi Shi, Chandler, AZ (US);
Tushar Talukdar, Wilsonville, OR (US);
Feras Eid, Chandler, AZ (US);
Mohammad Enamul Kabir, Portland, OR (US);
Omkar G. Karhade, Chandler, AZ (US);
Bhaskar Jyoti Krishnatreya, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.