The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Aug. 17, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Pavithra Sriram, Hsinchu, TW;
Kuo-Lung Pan, Hsinchu, TW;
PO-Yuan Teng, Hsinchu, TW;
Cheng-Chieh Wu, Taoyuan, TW;
Mao-Yen Chang, Kaohsiung, TW;
Yu-Chia Lai, Miaoli County, TW;
Shu-Rong Chun, Hsinchu County, TW;
Hao-Yi Tsai, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.