The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2025
Filed:
Jul. 15, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chansyun David Yang, Hsinchu, TW;
Huang-Lin Chao, Hsinchu, TW;
Hsiang-Pi Chang, Hsinchu, TW;
Yen-Tien Tung, Hsinchu, TW;
Chung-Liang Cheng, Hsinchu, TW;
Yu-Chia Liang, Hsinchu, TW;
Shen-Yang Lee, Hsinchu, TW;
Yao-Sheng Huang, Hsinchu, TW;
Tzer-Min Shen, Hsinchu, TW;
Pinyen Lin, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.