The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2025
Filed:
Dec. 21, 2021
Intel Corporation, Santa Clara, CA (US);
Jeremy Ecton, Gilbert, AZ (US);
Jason M. Gamba, Gilbert, AZ (US);
Brandon C. Marin, Chandler, AZ (US);
Srinivas V. Pietambaram, Chandler, AZ (US);
Xiaoxuan Sun, Phoenix, AZ (US);
Omkar G. Karhade, Chandler, AZ (US);
Xavier Francois Brun, Hillsboro, OR (US);
Yonggang Li, Chandler, AZ (US);
Suddhasattwa Nad, Chandler, AZ (US);
Bohan Shan, Tempe, AZ (US);
Haobo Chen, Chandler, AZ (US);
Gang Duan, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.