The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jul. 28, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuan-Kan Hu, Hsinchu, TW;

Jhih-Rong Huang, Hsinchu County, TW;

Yi-Bo Liao, Hsinchu, TW;

Shuen-Shin Liang, Hsinchu County, TW;

Min-Chiang Chuang, Taoyuan, TW;

Sung-Li Wang, Hsinchu County, TW;

Wei-Yen Woon, Taoyuan, TW;

Szuya Liao, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/285 (2006.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/28518 (2013.01); H10D 30/6219 (2025.01); H10D 62/151 (2025.01); H10D 64/62 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01);
Abstract

A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.


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