The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Urusa Alaan, Hillsboro, OR (US);

Abhishek A. Sharma, Portland, OR (US);

Charles C. Kuo, Union City, CA (US);

Benjamin Orr, Portland, OR (US);

Nicholas Thomson, Hillsboro, OR (US);

Ayan Kar, Portland, OR (US);

Arnab Sen Gupta, Hillsboro, OR (US);

Kaan Oguz, Beaverton, OR (US);

Brian S. Doyle, Portland, OR (US);

Prashant Majhi, San Jose, CA (US);

Van H. Le, Portland, OR (US);

Elijah V. Karpov, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H10D 89/60 (2025.01);
U.S. Cl.
CPC ...
H10D 89/60 (2025.01); H02H 9/046 (2013.01);
Abstract

Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.


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