The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2025
Filed:
Jun. 24, 2021
Intel Corporation, Santa Clara, CA (US);
William Hsu, Portland, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
Chung-Hsun Lin, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires; and a doped nucleation layer at a base of the epitaxial source or drain structures adjacent to the sub-fin. Where the integrated circuit structure comprises an NMOS transistor, doped nucleation layer comprises a carbon-doped nucleation layer. Where the integrated circuit structure comprises a PMOS transistor, doped nucleation layer comprises a heavy boron-doped nucleation layer.