The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jun. 17, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chin-Hua Wang, New Taipei, TW;

Shin-Puu Jeng, Hsinchu, TW;

Po-Yao Lin, Zhudong Township, Hsinchu County, TW;

Po-Chen Lai, Hsinchu County, TW;

Shu-Shen Yeh, Taoyuan, TW;

Ming-Chih Yew, Hsinchu, TW;

Yu-Sheng Lin, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/304 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 21/3043 (2013.01); H01L 23/3185 (2013.01); H01L 23/3192 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01);
Abstract

Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.


Find Patent Forward Citations

Loading…