The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2025
Filed:
Dec. 14, 2023
Intel Corporation, Santa Clara, CA (US);
Willy Rachmady, Beaverton, OR (US);
Cheng-Ying Huang, Portland, OR (US);
Matthew V. Metz, Portland, OR (US);
Nicholas G. Minutillo, Beaverton, OR (US);
Sean T. Ma, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).