The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Jan. 22, 2024
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ehren Mannebach, Beaverton, OR (US);

Aaron Lilak, Beaverton, OR (US);

Hui Jae Yoo, Portland, OR (US);

Patrick Morrow, Portland, OR (US);

Anh Phan, Beaverton, OR (US);

Willy Rachmady, Beaverton, OR (US);

Cheng-Ying Huang, Portland, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Rishabh Mehandru, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/8234 (2006.01); H01L 25/16 (2023.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/823412 (2013.01); H01L 21/823425 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 25/16 (2013.01); H01L 29/0653 (2013.01);
Abstract

Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.


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