The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Jul. 21, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Cheng-Ying Huang, Portland, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Aaron Lilak, Beaverton, OR (US);

Ehren Mannebach, Beaverton, OR (US);

Patrick Morrow, Portland, OR (US);

Anh Phan, Beaverton, OR (US);

Willy Rachmady, Beaverton, OR (US);

Hui Jae Yoo, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/311 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76264 (2013.01); H01L 21/02236 (2013.01); H01L 21/02252 (2013.01); H01L 21/02255 (2013.01); H01L 21/2253 (2013.01); H01L 21/2255 (2013.01); H01L 21/26533 (2013.01); H01L 21/266 (2013.01); H01L 21/31111 (2013.01); H01L 21/76267 (2013.01); H01L 29/0649 (2013.01); H01L 29/7853 (2013.01);
Abstract

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.


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