The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2024
Filed:
Sep. 25, 2020
Intel Corporation, Santa Clara, CA (US);
Han Wui Then, Portland, OR (US);
Marko Radosavljevic, Portland, OR (US);
Pratik Koirala, Portland, OR (US);
Nicole K. Thomas, Portland, OR (US);
Paul B. Fischer, Portland, OR (US);
Adel A. Elsherbini, Chandler, AZ (US);
Tushar Talukdar, Wilsonville, OR (US);
Johanna M. Swan, Scottsdale, AZ (US);
Wilfred Gomes, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Beomseok Choi, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.