The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2024

Filed:

Dec. 10, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sarah Atanasov, Beaverton, OR (US);

Abhishek A. Sharma, Hillsboro, OR (US);

Bernhard Sell, Portland, OR (US);

Chieh-Jen Ku, Portland, OR (US);

Elliot Tan, Portland, OR (US);

Hui Jae Yoo, Hillsboro, OR (US);

Noriyuki Sato, Hillsboro, OR (US);

Travis W. Lajoie, Forest Grove, OR (US);

Van H. Le, Beaverton, OR (US);

Thoe Michaelos, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10B 10/00 (2023.01); H10B 20/00 (2023.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H10B 12/31 (2023.02); H10B 10/12 (2023.02); H10B 20/27 (2023.02); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10B 63/34 (2023.02);
Abstract

Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.


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