The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Sep. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wensen Hung, Hsinchu County, TW;

Hsuan-Ning Shih, Taoyuan, TW;

Hsien-Pin Hu, Hsinchu County, TW;

Tsung-Shu Lin, New Taipei, TW;

Tsung-Yu Chen, Hsinchu, TW;

Wen-Hsin Wei, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 23/00 (2006.01); H01L 23/053 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/4817 (2013.01); H01L 21/4871 (2013.01); H01L 21/52 (2013.01); H01L 23/053 (2013.01); H01L 23/367 (2013.01);
Abstract

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.


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