The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wen-Kai Lin, Yilan County, TW;

Shih-Chiang Chen, Taichung, TW;

Po-Shao Lin, Taipei, TW;

Wei-Yang Lee, Taipei, TW;

Chia-Pin Lin, Hsinchu County, TW;

Yuan-Ching Peng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 29/0665 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.


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