The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Jul. 15, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aaron D. Lilak, Beaverton, OR (US);

Ehren Mannebach, Beaverton, OR (US);

Anh Phan, Beaverton, OR (US);

Richard E. Schenker, Portland, OR (US);

Stephanie A. Bojarski, Beaverton, OR (US);

Willy Rachmady, Beaverton, OR (US);

Patrick R. Morrow, Portland, OR (US);

Jeffrey D. Bielefeld, Forest Grove, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Hui Jae Yoo, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 23/481 (2013.01); H01L 23/53295 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/785 (2013.01);
Abstract

Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.


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