The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2024
Filed:
Sep. 23, 2020
Intel Corporation, Santa Clara, CA (US);
Daniel G. Ouellette, Portland, OR (US);
Daniel B. O'Brien, Beaverton, OR (US);
Jeffrey S. Leib, Beaverton, OR (US);
Orb Acton, Portland, OR (US);
Lukas Baumgartel, Portland, OR (US);
Dan S. Lavric, Beaverton, OR (US);
Dax M. Crum, Beaverton, OR (US);
Oleg Golonzka, Beaverton, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.