The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Dec. 20, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Zhiwei Gong, Chandler, AZ (US);

Li Li, Scottsdale, AZ (US);

Lu Li, Gilbert, AZ (US);

Lakshminarayan Viswanathan, Phoenix, AZ (US);

Fernando A. Santos, Chandler, AZ (US);

Burton Jesse Carpenter, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2223/6605 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01);
Abstract

Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.


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