The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2024
Filed:
May. 22, 2019
Intel Corporation, Santa Clara, CA (US);
Nidhi Nidhi, Hillsboro, OR (US);
Han Wui Then, Portland, OR (US);
Marko Radosavljevic, Portland, OR (US);
Sansaptak Dasgupta, Hillsboro, OR (US);
Paul B. Fischer, Portland, OR (US);
Rahul Ramaswamy, Portland, OR (US);
Walid M. Hafez, Portland, OR (US);
Johann Christian Rode, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.