The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2024
Filed:
Jun. 06, 2018
Intel Corporation, Santa Clara, CA (US);
Van H. Le, Portland, OR (US);
Inanc Meric, Portland, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Sean Ma, Portland, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Miriam Reshotko, Portland, OR (US);
Shriram Shivaraman, Hillsboro, OR (US);
Kent Millard, Hillsboro, OR (US);
Matthew V. Metz, Portland, OR (US);
Wilhelm Melitz, Portland, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Jack Kavalieros, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.