The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Feb. 25, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bok Eng Cheah, Bukit Gambir, MY;

Jenny Shio Yin Ong, Bayan Lepas, MY;

Seok Ling Lim, Kulim, MY;

Kooi Chi Ooi, Glugor, MY;

Jackson Chung Peng Kong, Tanjung Tokong, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01G 4/12 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01G 4/1272 (2013.01); H01L 23/5286 (2013.01); H01L 23/5381 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 28/60 (2013.01);
Abstract

An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.


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