The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Jun. 24, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsi-Wen Tien, Xinfeng Township, Hsinchu County, TW;

Wei-Hao Liao, Taichung, TW;

Yu-Teng Dai, New Taipei, TW;

Hsin-Chieh Yao, Hsinchu, TW;

Chih-Wei Lu, Hsinchu, TW;

Chung-Ju Lee, Hsinchu, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01);
Abstract

A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.


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