The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Jun. 14, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yi-Jing Lee, Hsinchu, TW;

Jeng-Wei Yu, Hsinchu, TW;

Li-Wei Chou, Hsinchu, TW;

Tsz-Mei Kwok, Hsinchu, TW;

Ming-Hua Yu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/84 (2013.01); H01L 27/0688 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01);
Abstract

A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.


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