The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Dec. 19, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nidhi Nidhi, Hillsboro, OR (US);

Rahul Ramaswamy, Portland, OR (US);

Sansaptak Dasgupta, Hillsboro, OR (US);

Han Wui Then, Portland, OR (US);

Marko Radosavljevic, Portland, OR (US);

Johann C. Rode, Hillsboro, OR (US);

Paul B. Fischer, Portland, OR (US);

Walid M. Hafez, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/15 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/155 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/7783 (2013.01); H01L 29/785 (2013.01);
Abstract

A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.


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