The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2024
Filed:
Sep. 28, 2018
Intel Corporation, Santa Clara, CA (US);
Jun Sung Kang, Portland, OR (US);
Kai Loon Cheong, Beaverton, OR (US);
Erica J. Thompson, Beaverton, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
William Hsu, Hillsboro, OR (US);
Dax M. Crum, Beaverton, OR (US);
Tahir Ghani, Portland, OR (US);
Bruce Beattie, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.