The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Jan. 19, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc Nanjing Company Limited, Nanjing, CN;
Han-Yu Lin, Nantou County, TW;
Fang-Wei Lee, Hsinchu, TW;
Kai-Tak Lam, Hsinchu, TW;
Raghunath Putikam, Hsinchu, TW;
Tzer-Min Shen, Hsinchu, TW;
Li-Te Lin, Hsinchu, TW;
Pinyen Lin, Rochester, NY (US);
Cheng-Tzu Yang, Hsinchu County, TW;
Tzu-Li Lee, Yunlin County, TW;
Tze-Chung Lin, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC NANJING COMPANY LIMITED, Nanjing, CN;
Abstract
A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.