The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Jul. 03, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Mao-Yen Chang, Kaohsiung, TW;

Chih-Wei Lin, Hsinchu County, TW;

Hao-Yi Tsai, Hsinchu, TW;

Kuo-Lung Pan, Hsinchu, TW;

Chun-Cheng Lin, New Taipei, TW;

Tin-Hao Kuo, Hsinchu, TW;

Yu-Chia Lai, Miaoli County, TW;

Chih-Hsuan Tai, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/73 (2013.01); H01L 21/568 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/17179 (2013.01); H01L 2224/17517 (2013.01); H01L 2224/26145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83007 (2013.01); H01L 2224/92125 (2013.01);
Abstract

A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.


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