The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2023
Filed:
Dec. 18, 2019
Intel Corporation, Santa Clara, CA (US);
Biswajeet Guha, Hillsboro, OR (US);
William Hsu, Hillsboro, OR (US);
Chung-Hsun Lin, Portland, OR (US);
Kinyip Phoa, Beaverton, OR (US);
Oleg Golonzka, Beaverton, OR (US);
Tahir Ghani, Portland, OR (US);
Kalyan Kolluru, Portland, OR (US);
Nathan Jack, Forest Grove, OR (US);
Nicholas Thomson, Hillsboro, OR (US);
Ayan Kar, Portland, OR (US);
Benjamin Orr, Munich, DE;
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.