The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2023
Filed:
Dec. 18, 2019
Intel Corporation, Santa Clara, CA (US);
Biswajeet Guha, Hillsboro, OR (US);
William Hsu, Hillsboro, OR (US);
Chung-Hsun Lin, Portland, OR (US);
Kinyip Phoa, Beaverton, OR (US);
Oleg Golonzka, Beaverton, OR (US);
Ayan Kar, Portland, OR (US);
Nicholas Thomson, Hillsboro, OR (US);
Benjamin Orr, Munich, DE;
Nathan Jack, Forest Grove, OR (US);
Kalyan Kolluru, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.