The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Jul. 15, 2019
Intel Corporation, Santa Clara, CA (US);
Jacob Vehonsky, Gilbert, AZ (US);
Nicholas S. Haehn, Scottsdale, AZ (US);
Thomas Heaton, Mesa, AZ (US);
Steve S. Cho, Chandler, AZ (US);
Rahul Jain, Gilbert, AZ (US);
Tarek Ibrahim, Mesa, AZ (US);
Antariksh Rao Pratap Singh, Gilbert, AZ (US);
Edvin Cetegen, Chandler, AZ (US);
Nicholas Neal, Scottsdale, AZ (US);
Sergio Chan Arguedas, Gilbert, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.