The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2023
Filed:
Jul. 16, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Po-Chen Lai, Hsinchu County, TW;
Chin-Hua Wang, New Taipei, TW;
Ming-Chih Yew, Hsinchu, TW;
Chia-Kuei Hsu, Hsinchu, TW;
Li-Ling Liao, Hsinchu, TW;
Po-Yao Lin, Hsinchu County, TW;
Shin-Puu Jeng, Po-Shan Village, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method for forming a chip package structure is provided. The method includes forming a dielectric layer over a redistribution structure. The redistribution structure includes a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The method includes forming a first conductive bump structure and a shield bump structure over the dielectric layer. The first conductive bump structure is electrically connected to the wiring layers, and the shield bump structure is electrically insulated from the wiring layers. The method includes bonding a first chip structure to the redistribution structure through the first conductive bump structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure extends across a first sidewall of the shield bump structure.