logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11723292 B1

PDFFull Text
Date of Patent:
Aug. 08, 2023

Filed:

Jun. 24, 2020

Rram cell structure with laterally offset beva/teva

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chih-Yang Chang, Yuanlin Township, TW;

Wen-Ting Chu, Kaohsiung, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Yu-Wen Liao, New Taipei, TW;

Hsia-Wei Chen, Taipei, TW;

Chin-Chieh Yang, New Taipei, TW;

Sheng-Hung Shih, Hsinchu, TW;

Wen-Chun You, Dongshan Township, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Grant S Withers

Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10N 70/8265 (2023.02); H10B 63/30 (2023.02); H10N 70/011 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/20 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); H10N 70/021 (2023.02); H10N 70/023 (2023.02); H10N 70/026 (2023.02); H10N 70/028 (2023.02); H10N 70/041 (2023.02); H10N 70/043 (2023.02); H10N 70/046 (2023.02); H10N 70/061 (2023.02); H10N 70/068 (2023.02); H10N 70/231 (2023.02); H10N 70/235 (2023.02); H10N 70/245 (2023.02); H10N 70/25 (2023.02); H10N 70/253 (2023.02); H10N 70/257 (2023.02); H10N 70/801 (2023.02); H10N 70/821 (2023.02); H10N 70/823 (2023.02); H10N 70/828 (2023.02); H10N 70/8413 (2023.02); H10N 70/8416 (2023.02); H10N 70/8418 (2023.02); H10N 70/8613 (2023.02); H10N 70/8616 (2023.02); H10N 70/881 (2023.02); H10N 70/882 (2023.02); H10N 70/883 (2023.02); H10N 70/884 (2023.02); H10N 70/8822 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02); H10N 70/8836 (2023.02); H10N 70/8845 (2023.02);
Abstract

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Find Patent Forward Citations

Loading…