The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Mar. 08, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wensen Hung, Hsinchu County, TW;

Ping-Kang Huang, Chiayi, TW;

Sao-Ling Chiu, Hsinchu, TW;

Tsung-Yu Chen, New Taipei, TW;

Tsung-Shu Lin, Hsinchu, TW;

Chien-Yuan Huang, Hsinchu, TW;

Chen-Hsiang Lao, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 23/42 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/4882 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 21/4871 (2013.01); H01L 23/42 (2013.01); H01L 25/0657 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.


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