The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2023
Filed:
Mar. 18, 2021
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Kuo Lung Pan, Zhunan Township, TW;
Yu-Chia Lai, Hsinchu, TW;
Tin-Hao Kuo, Hsinchu, TW;
Hao-Yi Tsai, Hsinchu, TW;
Chung-Shi Liu, Hsinchu, TW;
Chen-Hua Yu, Hsinchu, TW;
Po-Yuan Teng, Hsinchu, TW;
Teng-Yuan Lo, Hsinchu, TW;
Mao-Yen Chang, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Abstract
A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.