The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2023

Filed:

Jun. 15, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shu-Ting Tsai, Kaohsiung, TW;

Jeng-Shyan Lin, Tainan, TW;

Chun-Chieh Chuang, Tainan, TW;

Dun-Nian Yaung, Taipei, TW;

Jen-Cheng Liu, Hsinchu, TW;

Feng-Chi Hung, Chu-Bei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 27/06 (2006.01); H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01); A61N 1/39 (2006.01);
U.S. Cl.
CPC ...
A61N 1/3931 (2013.01); A61N 1/3987 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/53238 (2013.01); H01L 25/50 (2013.01); H01L 27/0688 (2013.01); H01L 27/14634 (2013.01); H01L 23/53257 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80894 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/9212 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01);
Abstract

A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.


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