The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2023
Filed:
Mar. 27, 2020
Intel Corporation, Santa Clara, CA (US);
Leonard P. Guler, Hillsboro, OR (US);
Stephen Snyder, Portland, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
William Hsu, Hillsboro, OR (US);
Urusa Alaan, Hillsboro, OR (US);
Tahir Ghani, Portland, OR (US);
Michael K. Harper, Hillsboro, OR (US);
Vivek Thirtha, Portland, OR (US);
Shu Zhou, Portland, OR (US);
Nitesh Kumar, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.