The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Feb. 22, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sansaptak Dasgupta, Hillsboro, OR (US);

Johann Christian Rode, Hillsboro, OR (US);

Han Wui Then, Portland, OR (US);

Marko Radosavljevic, Portland, OR (US);

Paul B. Fischer, Portland, OR (US);

Nidhi Nidhi, Hillsboro, OR (US);

Rahul Ramaswamy, Portland, OR (US);

Sandrine Charue-Bakker, Portland, OR (US);

Walid M. Hafez, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/26 (2006.01); H01L 21/8238 (2006.01); H01L 21/8258 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/8258 (2013.01); H01L 29/267 (2013.01); H01L 21/8238 (2013.01);
Abstract

Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.


Find Patent Forward Citations

Dasgupta, Sansaptak. (2023). Integration of iii-n transistors and non-iii-n transistors by semiconductor regrowth (U.S. Patent No. 11581313). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11581313

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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