The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2023
Filed:
May. 28, 2019
Applicant:
Apple Inc., Cupertino, CA (US);
Inventors:
Jun Chung Hsu, Taoyuan, TW;
Chih-Ming Chung, Cupertino, CA (US);
Jun Zhai, Cupertino, CA (US);
Yifan Kao, Taoyuan, TW;
Young Doo Jeon, San Jose, CA (US);
Taegui Kim, San Jose, CA (US);
Assignee:
Apple Inc., Cupertino, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/11003 (2013.01); H01L 2224/11424 (2013.01); H01L 2224/11464 (2013.01); H01L 2224/11614 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13164 (2013.01); H01L 2224/14517 (2013.01);
Abstract
Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.