The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Nov. 05, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bok Eng Cheah, Pinang, MY;

Seok Ling Lim, Kulim Kedah, MY;

Jackson Chung Peng Kong, Pinang, MY;

Jenny Shio Yin Ong, Pinang, MY;

Kooi Chi Ooi, Pinang, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/552 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49833 (2013.01); H01L 21/4803 (2013.01); H01L 21/4853 (2013.01); H01L 23/13 (2013.01); H01L 23/5385 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 23/552 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/1703 (2013.01);
Abstract

According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.


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