The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Sep. 22, 2020
Applicant:

Hefei Reliance Memory Limited, Hefei, CN;

Inventors:

Christophe J. Chevallier, Palo Alto, CA (US);

Steve Kuo-Ren Hsia, San Jose, CA (US);

Wayne Kinney, Emmett, ID (US);

Steven Longcor, Mountain View, CA (US);

Darrell Rinerson, Cupertino, CA (US);

John Sanchez, Palo Alto, CA (US);

Philip F. S. Swab, Santa Rosa, CA (US);

Edmond R. Ward, Monte Sereno, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); G11C 11/16 (2013.01); G11C 11/5685 (2013.01); G11C 13/0002 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 27/24 (2013.01); H01L 27/2463 (2013.01); H01L 27/2481 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/1633 (2013.01); H01L 45/1658 (2013.01); G11C 2013/009 (2013.01); G11C 2213/15 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/71 (2013.01); G11C 2213/77 (2013.01); G11C 2213/79 (2013.01);
Abstract

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.


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