The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2022
Filed:
Apr. 09, 2018
Intel Corporation, Santa Clara, CA (US);
Terrence Huat Hin Tan, Georgetown, MY;
Rehan Sheikh, Austin, TX (US);
Michael T. Klinglesmith, Portland, OR (US);
Sukhbinder Takhar, Portland, OR (US);
Shi Hou Chong, Penang, MY;
Kok Hin Oon, Bayan Lepas, MY;
Wai Loon Yip, Penang, MY;
Yudhishthira Kundu, Bangalore, IN;
Deepak R. Tanna, Doddennakundi Village, IN;
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.