The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Feb. 13, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aaron D. Lilak, Beaverton, OR (US);

Ehren Mannebach, Beaverton, OR (US);

Anh Phan, Beaverton, OR (US);

Richard Schenker, Portland, OR (US);

Stephanie A. Bojarski, Beaverton, OR (US);

Willy Rachmady, Beaverton, OR (US);

Patrick Morrow, Portland, OR (US);

Jeffery Bielefeld, Forest Grove, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Hui Jae Yoo, Hillsboro, OR (US);

Nafees Kabir, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 23/522 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/02603 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a 'jogged via' establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.


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